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a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 rev. a AD7490 16-channel, 1 msps, 12-bit adc with sequencer in 28-lead tssop functional block diagram v in 0 v in 15 t/h i/p mux sequencer control logic 12-bit successive approximation adc gnd sclk dout din cs v drive v dd AD7490 ref in features fast throughput rate: 1 msps specified for v dd of 2.7 v to 5.25 v low power at max throughput rates: 5.4 mw max at 870 ksps with 3 v supplies 12.5 mw max at 1 msps with 5 v supplies 16 (single-ended) inputs with sequencer wide input bandwidth: 69.5 db snr at 50 khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface spi ? /qspi ? / microwire ? /dsp compatible full shutdown mode: 0.5 a max 28-lead tssop and 32-lead lfcsp packages general description the AD7490 is a 12-bit high speed, low power, 16-channel, successive-approximation adc. the part operates from a single 2.7 v to 5.25 v power supply and features throughput rates up to 1 msps. the part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 1 mhz. the conversion process and data acquisition are controlled using cs and the serial clock signal, allowing the device to easily interface with microprocessors or dsps. the input signal is sampled on the falling edge of cs and conversion is also initiated at this point. there are no pipeline delays associated with the part. the AD7490 uses advanced design techniques to achieve very low power dissipation at high throughput rates. for maximum throughput rates, the AD7490 consumes just 1.8 ma with 3 v supplies, and 2.5 ma with 5 v supplies. by setting the relevant bits in the control register, the analog input range for the part can be selected to be a 0 to ref in input or a 0 to 2 ref in with either straight binary or twos complement output coding. the AD7490 features 16 single-ended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially. the conversion time is determined by the sclk frequency as this is also used as the master clock to control the conversion. the AD7490 is available in a 28-lead thin shrink small outline (tssop) package, and a 32-lead chip scale package. spi and qspi are trademarks of motorola inc. microwire is a trademark of national semiconductor corporation product highlights 1. high throughput with low power consumption the AD7490 offers up to 1 msps throughput rates. at maximum throughput with 3 v supplies, the AD7490 dissipates just 5.4 mw of power. 2. sixteen single-ended inputs with channel sequencer a sequence of channels can be selected, through which the AD7490 will cycle and convert. 3. single-supply operation with v drive function the AD7490 operates from a single 2.7 v to 5.25 v supply. the v drive function allows the serial interface to connect directly to either 3 v or 5 v processor systems independent of v dd . 4. flexible power/serial clock speed management the conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. the part also features various shutdown modes to maximize power efficiency at lower throughput rates. power consumption is 0.5 a max when in full shutdown. 5. no pipeline delay the part features a standard successive-approximation adc with accurate control of the sampling instant via a cs input and once off conversion control.
? AD7490?pecifications rev. a (v dd = v drive = 2.7 v to 5.25 v, ref in = 2.5 v, f sclk 1 = 20 mhz, t a = t min to t max , unless otherwise noted.) parameter b version 2 unit test conditions/comments dynamic performance f in = 50 khz sine wave, f sclk = 20 mhz signal to noise +1 distortion (sinad) 3 69 db min @ 5 v, 70.5 db typ 68 db min @ 3 v, 69.5 db typ signal to noise ratio (snr) 3 69.5 db min total harmonic distortion (thd) 3 C 74 db max @ 5 v, C 84 db typ C 71 db max @ 3 v, C 77 db typ peak harmonic or spurious noise (sfdr) 3 C 75 db max @ 5 v, C 86 db typ C 73 db max @ 3 v, C 80 db typ intermodulation distortion (imd) 3 fa = 40.1 khz, fb = 41.5 khz second order terms C 85 db typ third order terms C 85 db typ aperture delay 10 ns typ aperture jitter 50 ps typ channel-to-channel isolation 3 C 82 db typ f in = 400 khz full power bandwidth 8.2 mhz typ @ 3 db 1.6 mhz typ @ 0.1 db dc accuracy 3 resolution 12 bits integral nonlinearity 1 lsb max differential nonlinearity C 0.95/+1.5 lsb max guaranteed no missed codes to 12 bits 0v to v ref in input range straight binary output coding offset error 8 lsb max 0.6 lsb typ offset error match 0.5 lsb max gain error 2 lsb max gain error match 0.6 lsb max 0v to 2 v ref in input range C v ref in to +v ref in biased about v ref w ith twos complement output coding offset positive gain error 2 lsb max positive gain error match 0.5 lsb max zero code error 8 lsb max 0.6 lsb typ zero code error match 0.5 lsb max negative gain error 1 lsb max negative gain error match 0.5 lsb max analog input input voltage ranges 0 to ref in v range bit set to 1 0 to 2 ref in v range bit set to 0, v dd /v drive = 4.75 v to 5.25 v for 0 to 2 ref in dc leakage current 1 a max input capacitance 20 pf typ reference input ref in input voltage 2.5 v 1% specified performance dc leakage current 1 a max ref in input impedance 36 k ? typ f sample = 1 msps logic inputs input high voltage, v inh 0.7 v drive v min input low voltage, v inl 0.3 v drive v max input current, i in 1 a max typically 10 na, v in 5 0 v or v drive input capacitance, c in 4 10 pf max logic outputs output high voltage, v oh v drive C 0.2 v min i source = 200 a; v dd = 2.7 v to 5.25 v output low voltage, v ol 0.4 v max i sink = 200 a floating-state leakage current 10 a max weak/ tri bit set to 0 floating-state output capacitance 4 10 pf max weak/ tri bit set to 0 output coding straight (natural) binary coding bit set to 1 twos complement coding bit set to 0
AD7490 ? rev. a parameter b version 2 unit test conditions/comments conversion rate conversion time 800 ns max 16 sclk cycles, sclk = 20 mhz track-and-hold acquisition time 3 300 ns max sine wave input 300 ns max full-scale step input throughput rate 1 msps max @ 5 v (see serial interface section.) power requirements v dd 2.7/5.25 v min/max v drive 2.7/5.25 v min/max i dd 5 digital i/ps = 0 v or v drive normal mode (static) 600 a typ v dd = 2.7 v to 5.25 v, sclk on or off normal mode (operational) 2.5 ma max v dd = 4.75 v to 5.25 v, f sclk = 20 mhz (f s = max throughput) 1.8 ma max v dd = 2.7 v to 3.6 v, f sclk = 20 mhz auto standby mode 1.55 ma typ f sample = 500 ksps 92 a max static auto shutdown mode 960 a typ f sample = 250 ksps 0.5 a max static full shutdown mode 0.5 a max sclk on or off (20 na typ) power dissipation 5 normal mode (operational) 12.5 mw max v dd = 5 v, f sclk = 20 mhz 5.4 mw max v dd = 3 v, f sclk = 20 mhz auto standby mode (static) 460 w max v dd = 5 v 276 w max v dd = 3 v auto shutdown mode (static) 2.5 w max v dd = 5 v 1.5 w max v dd = 3 v full shutdown mode 2.5 w max v dd = 5 v 1.5 w max v dd = 3 v notes 1 specifications apply for f sclk up to 20 mhz. however, for serial interfacing requirements, see timing specifications. 2 temperature ranges (b version): C 40 c to +85 c. 3 see terminology section. 4 sample tested at 25 c to ensure compliance. 5 see power versus throughput rate section. specifications subject to change without notice.
? AD7490 rev. a timing specifications 1 limit at t min , t max parameter v dd = 3 v v dd = 5 v unit description f sclk 2 10 10 khz min 16 20 mhz max t convert 16 t sclk 16 t sclk t quiet 50 50 ns min minimum quiet time required between bus relinquish and start of next conversion t 2 12 10 ns min cs to sclk setup time t 3 3 20 14 ns max delay from cs until dout three-state disabled t 3 b 4 30 20 ns max delay from cs to dout valid t 4 3 60 40 ns max data access time after sclk falling edge t 5 0.4 t sclk 0.4 t sclk ns min sclk low pulsewidth t 6 0.4 t sclk 0.4 t sclk ns min sclk high pulsewidth t 7 15 15 ns min sclk to dout valid hold time t 8 5 15/50 15/50 ns min/max sclk falling edge to dout high impedance t 9 20 20 ns min din setup time prior to sclk falling edge t 10 55 ns min din hold time after sclk falling edge t 11 20 20 ns min sixteenth sclk falling edge to cs h igh t 12 11 s max power-up time from full power-down/ auto shutdown/auto standby modes notes 1 sample tested at 25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. (see figure 1.) the 3 v operating range spans from 2.7 v to 3.6 v. the 5 v operating range spans from 4.75 v to 5.25 v. 2 mark/space ratio for the sclk input is 40/60 to 60/40. the maximum sclk frequency is 16 mhz with v dd = 3 v to give a throughput of 870 ksps. care must be taken when interfacing to account for data access time t 4 , and the setup time required for the user s processor. these two times will determine the maximum sclk frequency with which the user s system can operate. (see serial interface section.) 3 measured with the load circuit of figure 1 and defined as the time required for the output to cross 0.4 v or 0.7 v drive v. 4 t 3 b represents a worst-case figure for having add3 available on the dout line, i.e., if the AD7490 went back into three-state at the end of a conversion and some other device took control of the bus between conversions, the user would have to wait a maximum time of t 3 b before having add3 valid on dout line. if the dout line is weakly driven to add3 between conversions, then the user would typically have to wait 17 ns at 3 v and 12 ns at 5 v aft er the cs falling edge before seeing add3 valid on dout. 5 t 8 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the measu red number is then extrapolated back to remove the effects of charging or discharging the 25 pf capacitor. this means that the time, t 8 , quoted in the timing characteristics, is the true bus relinquish time of the part and is independent of the bus loading. specifications subject to change without notice. (v dd = 2.7 v to 5.25 v, v drive v dd , ref in = 2.5 v; t a = t min to t max , unless otherwise noted.)
AD7490 ? rev. a absolute maximum ratings 1 (t a = 25 c, unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C 0.3 v to +7 v v drive to gnd . . . . . . . . . . . . . . . . . . C 0.3 v to v dd + 0.3 v analog input voltage to gnd . . . . . . . C 0.3 v to v dd + 0.3 v digital input voltage to gnd . . . . . . . . . . . . . C 0.3 v to +7 v digital output voltage to gnd . . . . . C 0.3 v to v dd + 0.3 v ref in to gnd . . . . . . . . . . . . . . . . . . C 0.3 v to v dd + 0.3 v input current to any pin except supplies 2 . . . . . . . . 10 ma operating temperature ranges commercial (b version) . . . . . . . . . . . . . . C 40 c to +85 c storage temperature range . . . . . . . . . . . C 65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c i ol i oh 1.6v to output pin c l 25pf 200 a 200 a figure 1. load circuit for digital output timing specifications lfcsp, tssop package, power dissipation . . . . . . 450 mw ja thermal impedance . . . . . . . . . . . 108.2 c/w (lfcsp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97.9 c/w (tssop) jc thermal impedance . . . . . . . . . . . 32.71 c/w (lfcsp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 c/w (tssop) lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220 c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kv notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch up. ordering guide temperature linearity package package model range error (lsb) 1 option description AD7490bcp C 40 c to +85 c 1 cp-32 lfcsp AD7490bru C 40 c to +85 c 1 ru-28 tssop eval-AD7490cb 2 evaluation board eval-control brd2 3 controller board notes 1 linearity error refers to integral linearity error. 2 this can be used as a stand-alone evaluation board or in conjunction with the evaluation controller board for evaluation/ demonstration purposes. 3 this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. to order a complete evaluation kit, you will need to order the particular adc evaluation board, e.g., eval-AD7490cb, the eval-control-brd2, and a 12 v ac transformer. see relevant evaluation board technical note for more information. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7490 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
? AD7490 rev. a 28-lead tssop pin function descriptions mnemonic function cs chip select. active low logic input. this input provides the dual function of initiating conversions on the AD7490 and also frames the serial data transfer. ref in reference input for the AD7490. an external reference must be applied to this input. the voltage range for the external reference is 2.5 v 1% for specified performance. v dd power supply input. the v dd range for the AD7490 is from 2.7 v to 5.25 v. for the 0 to 2 ref in range, v dd should be from 4.75 v to 5.25 v. agnd analog ground. ground reference point for all circuitry on the AD7490. all analog/digital input signals and any external reference signal should be referred to this agnd voltage. all agnd pins should be connected together. v in 0 C v in 15 analog input 0 through analog input 15. sixteen single-ended analog input channels that are multiplexed into the on-chip track-and-hold. the analog input channel to be converted is selected by using the ad dress bits add3 through add0 of the control register. the address bits in conjunction with the seq and shadow bits allow the sequence register to be programmed. the input range for all input channels can extend from 0 v to ref in or 0 v to 2 ref in as selected via the range bit in the control register. any unused input channels should be connected to agnd to avoid noise pickup. din data in. logic input. data to be written to the AD7490 s control register is provided on this input and is clocked into the register on the falling edge of sclk (see control register section). dout data out. logic output. the conversion result from the AD7490 is provided on this output as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream consists of four address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, which is provided msb first. the output coding may be selected as straight binary or twos complement via the coding bit in the control register. sclk serial clock. logic input. sclk provides the serial clock for accessing data from the part. this clock input is also used as the clock source for the AD7490 s conversion process. v drive logic power supply input. the voltage supplied at this pin determines at what voltage the serial interface of the AD7490 will operate. 32-lead lfcsp top view (not to scale) nc a gnd ref in v dd a gnd cs nc v in 8 v in 7 v in 6 v in 5 v in 4 v in 3 nc nc v in 9 v in 10 v in 12 v in 13 v in 14 v in 2 v in 1 v in 0 a gnd dout sclk v drive nc = no connect v in 15 v in 11 AD7490 nc din nc 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 32 31 30 2 9 28 27 26 25 exposed pad should be tied to agnd top view (not to scale) pin configurations * * all nc pins should be connected straight to agnd top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AD7490 nc = no connect agnd v in 0 v in 1 v in 2 v in 3 v in 4 v in 5 v in 11 v in 10 v in 9 nc v in 6 v in 7 v in 8 dout sclk v drive nc din cs agnd v in 12 v in 13 v in 14 v in 15 v dd ref in agnd
AD7490 ? rev. a terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 000) to (00 001) from the ideal, i.e., agnd 1 lsb. offset error match this is the difference in offset error between any two channels. gain error this is the deviation of the last code transition (111 110) to (111 111) from the ideal (i.e., ref in 1l sb) after the offset error has been adjusted out. gain error match this is the difference in gain error between any two channels. zero code error this applies when using the twos complement output coding option, in particular to the 2 ref in input range with C ref in to +ref in biased about the ref in point. it is the deviation of the midscale transition (all 0s to all 1s) from the ideal v in voltage, i.e., ref in C 1 lsb. zero code error match this is the difference in zero code error between any two channels. positive gain error this applies when using the twos complement output coding option, in particular to the 2 ref in input range with C ref in to +ref in biased about the ref in point. it is the deviation of the last code transition (011 110) to (011 111) from the ideal (i.e., +ref in 1 lsb) after the zero code error has been adjusted out. positive gain error match this is the difference in positive gain error between any two channels. negative gain error this applies when using the twos complement output coding option, in particular to the 2 ref in input range with C ref in to +ref in biased about the ref in point. it is the deviation of the first code transition (100 000) to (100 001) from the ideal (i.e., C ref in + 1 lsb) after the zero code error has been adjusted out. negative gain error match this is the difference in negative gain error between any two channels. channel-to-channel isolation channel-to-channel isolation is a measure of the level of cross- talk between channels. it is measured by applying a full-scale 400 khz sine wave signal to all 15 nonselected input channels and determining how much that signal is attenuated in the selected channel with a 50 khz signal. the figure is given worst case across all 16 channels for the AD7490. psr (power supply rejection) variations in power supply will affect the full scale transition, but not the converter s linearity. power supply rejection is the maximum change in full-scale transition point due to a change in power- supply voltage from the nominal value. (see typical performance c haracteristics.) track/hold acquisition time the track/hold amplifier returns into track on the 14th sclk falling edge. track/hold acquisition time is the minimum time required for the track and hold amplifier to remain in track mode for its output to reach and settle to within 1 lsb of the applied input signal, given a step change to the input signal. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitiza- tion process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to noise distortion n db ()(..) +=+ 602 176 thus for a 12-bit converter, this is 74 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the AD7490, it is defined as: thd db vvvvv v () log = ++++ 20 2 2 3 2 4 2 5 2 6 2 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the har- monics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). the AD7490 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs.
? AD7490?ypical performance characteristics rev. a tpc 1 shows a typical fft plot for the AD7490 at 1 msps sample rate and 50 khz input frequency. tpc 3 shows the power supply rejection ratio versus supply ripple frequency for the AD7490. the power supply rejection ratio is defined as the ratio of the power in the adc output at full-scale frequency f, to the power of a 200 mv p-p sine wave applied to the adc v dd supply of frequency f s . psrr db pf pf s () log = ? ? ? ? ? ? 10 pf is equal to the power at frequency f in adc output; pf s is equal to power at frequency f s coupled onto the adc v dd supply input. here, a 200 mv p-p sine wave is coupled onto the v dd supply. 10 nf decoupling was used on the supply and a 1 f decoupling cap on the ref in pin. input frequency ?hz ?0 ?0 01m 100k psrr ?db 200k 300k 400k 500k 600k 700k 800k 900k ?0 ?0 ?0 ?0 ?0 ?0 v dd 5v v dd 3v v dd 3v/5v, 10nf cap 200mv p-p sine wave on v dd ref in 2.5v, 1 f cap t a 25 c tpc 3. psrr vs. supply ripple frequency input frequency ?khz ?0 ?0 10 1000 100 thd ?db ?0 ?0 ?0 v dd v drive 4.75v v dd v drive 5.25v v dd v drive 2.7v v dd v drive 3.6v f s max throughput t a 25 c range 0 to ref in ?5 ?5 ?5 ?5 tpc 4. thd vs. analog input frequency for various supply voltages at 1 msps input frequency ?khz ?0 10 1000 100 thd ?db ?0 ?0 ?0 r in 100 f s 1 msps t a 25 c v dd 5.25 v range 0 to ref in ?5 ?5 ?5 ?5 r in 1000 r in 10 r in 50 r in 1000 tpc 5. thd vs. analog input frequency for various analog source impedances 5 ?5 ?15 snr ?db ?5 ?5 ?5 ?5 frequency ?khz 0 500 50 100 150 200 250 300 350 400 450 8192 point fft f sample 1msps f in 50khz sinad 70.697db thd ?9.171db sfdr ?9.93db tpc 1. dynamic performance at 1 msps input frequency ?khz 75 55 10 1000 100 sinad ?db 65 70 60 v dd v drive 5.25v v dd v drive 4.75v v dd v drive 2.7v v dd v drive 3.6v f s max throughput t a 25 c range 0 to ref in tpc 2. sinad vs. analog input frequency for various supply voltages at 1 msps
AD7490 ? rev. a code 1.0 ?.0 0 4096 512 inl error ?lsb 1024 1536 2048 2560 3072 3584 0.8 0.2 ?.2 ?.6 ?.8 0.6 0.4 0 ?.4 v dd v drive 5v temp 25 c tpc 6. typical inl control register the control register on the AD7490 is a 12-bit, write-only register. data is loaded from the din pin of the AD7490 on the falli ng edge of sclk. the data is transferred on the din line at the same time as the conversion result is read from the part. the data transferred on the din line corresponds to the AD7490 configuration for the next conversion. this requires 16 serial clocks for every data transfer. only the information provided on the first 12 falling clock edges (after cs falling edge) is loaded to the control register. msb denotes the first bit in the data stream. the bit functions are outlined in table i. table i. control register bit functions b s m b s l e t i r wq e s3 d d a2 d d a1 d d a0 d d a1 m p0 m pw o d a h si r t / k a e we g n a rg n i d o c bit name description 11 write the value written to this bit of the control register determines whether the following 11 bits will be loaded to the control register or not. if this bit is a 1, the following 11 bits will be written to the control register; if it is a 0, the remaining 11 bits are not loaded to the control register and so it remains unchanged. 10 seq the seq bit in the control register is used in conjunction with the shadow bit to control the use of the sequencer function and access the shadow register. (see table iv.) 9 C 6a dd3 C add0 these four address bits are loaded at the end of the present conversion sequence, and select which analog input channel is to be converted on in the next serial transfer, or may select the final channel in a con- secutive sequence as described in table iv. the selected input channel is decoded as shown in table ii. the address bits corresponding to the conversion result are also output on dout prior to the 12 bits of data (see serial interface section). the next channel to be converted on will be selected by the mux on the 14th sclk falling edge. 5, 4 pm 1, pm0 power management bits. these two bits decode the mode of operation of the AD7490 as shown in table iii. 3 shadow the shadow bit in the control register is used in conjunction with the seq bit to control the use of the sequencer function and access the shadow register. (see table iv.) 2 weak/ tri this bit selects the state of the dout line at the end of the current serial transfer. if it is set to 1, the dout line will be weakly driven to the channel address bit add3 of the ensuing conversion. if this bit is set to 0, then dout will return to three-state at the end of the serial transfer. see the serial interface section for more details. 1 range this bit selects the analog input range to be used on the AD7490. if it is set to 0, then the analog input range will extend from 0 v to 2 ref in . if it is set to 1, then the analog input range will extend from 0 v to ref in (for the next conversion). for 0 v to 2 ref in , v dd = 4.75 v to 5.25 v. 0 coding this bit selects the type of output coding the AD7490 will use for the conversion result. if this bit is set to 0, the output coding for the part will be twos complement. if this bit is set to 1, the output coding from the part will be straight binary (for the next conversion). code 1.0 ?.0 0 4096 512 dnl error ?lsb 1024 1536 2048 2560 3072 3584 0.8 0.2 ?.2 ?.6 ?.8 0.6 0.4 0 ?.4 v dd v drive 5v temp 25 c tpc 7. typical dnl
?0 AD7490 rev. a table ii. channel selection analog input add3 add2 add1 add0 channel 0000v in 0 0001v in 1 0010v in 2 0011v in 3 0100v in 4 0101v in 5 0110v in 6 0111v in 7 1000v in 8 1001v in 9 1010v in 10 1011v in 11 1100v in 12 1101v in 13 1110v in 14 1111v in 15 table iii. power mode selection pm1 pm0 mode 11 normal operation in this mode, the AD7490 remains in full power mode regardless of the status of any of the logic inputs. this mode allows the fastest possible throughput rate from the AD7490. 10 full shutdown in this mode, the AD7490 is in full shut-down mode, with all circuitry on the AD7490 powering down. the AD7490 retains the information in the control register while in full shutdown. the part remains in full shutdown until these bits are changed in the control register. 01 auto shutdown in this mode, the AD7490 automatically enters shutdown mode at the end of each conversion when the control register is updated. wake-up time from shutdown is 1 s and the user should ensure that 1 s has elapsed before attempting to perform a valid conversion on the part in this mode. 00 auto standby in this standby mode, portions of the AD7490 are powered down, but the on-chip bias gen- erator remains powered-up. this mode is similar to auto shutdown and allows the part to power-up within one dummy cycle, i.e., 1 s with a 20 mhz sclk. for more information, see the modes of operation section. sequencer operation the configuration of the seq and s hadow bits in the control register allows the user to select a particular mode of operation of the sequencer function. table iv outlines the four modes of operation of the sequencer. table iv. sequence selection seq shadow sequence type 00 this configuration means the sequence function is not used. the analog input channel selected for each individual conversion is determined by the contents of the channel address bits add0 through add3 in each prior write operation. this mode of operation reflects the normal operation of a multichannel adc, without sequencer function being used, where each write to the AD7490 selects the next channel for conversion. (see figure 2.) 01 this configuration selects the shadow register for programming. after the write to the control register, the following write operation will load the contents of the shadow register. this will program t he sequence of channels to be converted on continuously with each successive valid cs falling edge. (see shadow regis- ter, table v, and figure 3.) the channels selected need not be consecutive. 10 if the seq and shadow bits are set in this way, then the sequence function will not be interrupted upon completion of the write operation. this allows other bits in the control register to be altered w hile in a sequence without terminating the cycle. 11 this configuration is used in conjunction with the channel address bits add3 to add0 to program continuous conver- sions on a consecutive sequence of channels from channel 0 through to a selected final channel as determined by the channel address bits in the control register. (see figure 4.)
AD7490 ?1 rev. a shadow register the shadow register on the AD7490 is a 16-bit, write-only register. data is loaded from the din pin of the AD7490 on the fallin g edge of sclk. the data is transferred on the din line at the same time as a conversion result is read from the part. this requi res 16 serial falling edges for the data transfer. the information is clocked into the shadow register provided the seq and s hadow b its were set to 0, 1 respectively in the previous write to the control register. msb denotes the first bit in the data stream. each bit represe nts an analog input from channel 0 through to channel 15. a sequence of channels may be selected through which the AD7490 will cycle w ith each consecutive cs falling edge after the write to the shadow register. to select a sequence of channels, the associated channel bit must be set for each analog input. the AD7490 will continuously cycle through the selected channels in ascending order, beginni ng with the lowest channel, until a write operation occurs (i.e., the write bit is set to 1) with the seq and shadow bits configur ed in any way except 1, 0 (see table iv). the bit functions are outlined in table v. table v. shadow register bit functions b s m b s l v n i 0v n i 1v n i 2v n i 3v n i 4v n i 5v n i 6v n i 7v n i 8v n i 9v n i 0 1v n i 1 1v n i 2 1v n i 3 1v n i 4 1v n i 5 1 power on dummy conversions din = all 1s din: write to control register, write bit = 1, select coding, range, and power mode select channel a3?0 for conversion, seq = shadow = 0 dout: conversion result from previously selected channel a3?0 din: write to control register, write bit = 1, select coding, range, and power mode select a3?0 for conversion, seq = shadow = 0 write bit = 1, seq = shadow = 0 cs cs figure 2. seq bit = 0, shadow bit = 0 flowchart figure 2 reflects the normal operation of a multichannel adc, where each serial transfer selects the next channel for conversion. in this mode of operation, the sequencer function is not used. figure 3 shows how to program the AD7490 to continuously con- vert on a particular sequence of channels. to exit this mode of operation and revert back to the normal mode of operation of a multichannel adc (as outlined in figure 2), ensure the write bit = 1 and the seq = shadow = 0 on the next serial transfer. power on dummy conversions din = all 1s din: write to control register, write bit = 1, select coding, range, and power mode select channel a3?0 for conversion, seq = 0 shadow = 1 dout: conversion result from previously selected channel a3?0 din: write to shadow register, selecting which channels to convert on; channels selected need not be consecutive write bit = 1, seq = 1, shadow = 0 continuously converts on the selected sequence of channels continuously converts on the selected sequence of channels but will allow range, coding, and so on, to change in the control register without interrupt- ing the sequence provided, seq = 1 shadow = 0 write bit = 0 write bit = 0 write bit = 1, seq = 1, shadow = 0 write bit = 0 cs cs cs figure 3. seq bit = 0, shadow bit = 1 flowchart
?2 AD7490 rev. a figure 4 shows how a sequence of consecutive channels can be converted on without having to program the shadow register or write to the part on each serial transfer. again, to exit this mode of operation and revert back to the normal mode of operation of a multichannel adc (as outlined in figure 2), ensure the write bit = 1 and the seq = shadow = 0 on the next serial transfer. power on dummy conversions din = all 1s din: write to control register, write bit = 1, select coding, range, and power mode select channel a3?0 for conversion, seq = 1 shadow = 1 dout: conversion result from channel 0 continuously converts on a consecutive sequence of channels from channel 0 up to and including the previously selected a3?0 in the control register write bit = 0 continuously converts on the selected sequence of channels but will allow range, coding, and so on, to change in the control register without interrupting the sequence provided, seq = 1, shadow = 0 write bit = 1, seq = 1, shadow = 0 cs cs cs write bit = 1, seq = 1, shadow = 0 figure 4. seq bit = 1, shadow bit = 1 flowchart circuit information the AD7490 is a fast, 16-channel, 12-bit, single-supply, a/d conver- ter. the parts can be operated from a 2.7 v to 5.25 v supply. when operated from a 5 v supply, the AD7490 is capable of throughput rates of up to 1 msps when provided with a 20 mhz clock. the AD7490 provides the user with an on-chip track/hold, a/d converter, and a serial interface housed in either 28-lead tssop or 32-lead lfcsp package. the AD7490 has 16 single-ended input channels with a channel sequencer, allowing the user to select a sequence of channels through which the adc can cycle with each consecutive cs falling edge. the serial clock input accesses data from the part, controls the transfer of data written to the adc, and provides the clock source for the successive-approximation a/d converter. the analog input range for the ad74790 is 0 to ref in or 0 to 2 ref in depending on the status of bit 1 in the control register. for the 0 to 2 ref in range, the part must be operated from a 4.75 v to 5.25 v supply. the AD7490 provides flexible power management options to allow the user to achieve the best power performance for a given throughput rate. these options are selected by programming the power management bits in the control register. converter operation the AD7490 is a 12-bit successive approximation analog-to-digital converter based around a capacitive dac. the AD7490 can convert analog input signals in the range 0 v to v ref in or 0 v to 2 v ref in . figures 5 and 6 show simplified schematics of the adc. the adc comprises control logic, sar, and a capacitive dac, which are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. figure 5 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a. the comparator is held in a balanced condition and the sampling capacitor acquires the signal on the selected v in channel. v in 0 . . v in 15 a gnd a b sw1 sw2 comparator control logic capacitive dac 4k figure 5. adc acquisition phase when the adc starts a conversion (see figure 6), sw2 will open and sw1 will move to position b causing the comparator to become unbalanced. the control logic and the capacitive dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. figure 8 shows the adc transfer function. v in 0 . . v in 15 a gnd a b sw1 sw2 comparator control logic 4k capacitive dac figure 6. adc conversion phase analog input figure 7 shows an equivalent circuit of the analog input structure of the AD7490. the two diodes, d1 and d2, provide esd pro- tection for the analog inputs. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mv. this will cause these diodes to become forward biased and start conducting current into the substrate. 10 ma is the maximum current these diodes can conduct without causing irre versible damage to the part. the capacitor c1 in figure 7 is typically about 4 pf and can primarily be attributed to pin capacitance. the resistor r1 is a lumped component made up of v in c1 4pf c2 30pf r1 d1 d2 v dd conversion phase?witch open track phase?witch closed figure 7. equivalent analog input circuit
AD7490 ?3 rev. a the on resistance of a switch (track and hold switch) and also includes the on resistance of the input multiplexer. the total resistance is typically about 400 ? . the capacitor c2 is the adc sampling capacitor and typically has a capacitance of 30 pf. for ac appli- cations, removing high frequency components from the analog input signal is recommended by use of an rc low-pass filter on the relevant analog input pin. in applications where harmonic distor- tion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances will significantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of the op amp will be a function of the particular application. when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance will depend on the amount of total harmonic distortion (thd) that can be tolerated. the thd will increase as the source impedance increases, and performance will degrade (see tpc 5). adc transfer function the output coding of the AD7490 is either straight binary or twos complement depending on the status of the lsb (range bit) in the control register. the designed code transitions occur midway between successive lsb values (i.e., 1 lsb, 2 lsbs, and so on). the lsb size is equal to ref in /4096. the ideal transfer charac- ter istic for the AD7490 when straight binary coding is selected is shown in figure 8. 000?00 0v analog input 111?11 000?01 000?10 111?10 111?00 011?11 1 lsb +v ref 1 lsb 1 lsb v ref /4096 v ref is either ref in or 2 ref in figure 8. straight binary transfer characteristic v ref r3 r2 r4 r1 ref in v in 0 v in 15 AD7490 dsp/ p v dd 0.1 f v v dd v drive dout twos complement +ref in ( 2 ref in ) ref in ?ef in ( 0v) 011?11 000?00 100?00 0v v r1 r2 r3 r4 figure 10. handling bipolar signals ? ref 1 lsb adc code analog input +v ref 1 lsb 1 lsb 2 v ref 4096 v ref 1 lsb 100?00 011?11 100?01 100?10 011?10 000?01 111?11 000?00 figure 9. twos complement transfer characteristic with ref in ref in input range handling bipolar input signals figure 10 shows how useful the combination of the 2 ref in input range and the twos complement output coding scheme is for handling bipolar input signals. if the bipolar input signal is biased about ref in and twos complement output coding is selected, then ref in becomes the zero code point, C ref in is negative fullscale and +ref in becomes positive full scale, with a dynamic range of 2 ref in . typical connection diagram figure 11 shows a typical connection diagram for the AD7490. in this setup, the agnd pin is connected to the analog ground plane of the system. in figure 11, ref in is connected to a decoupled 2.5 v supply from a reference source, the ad780, to provide an analog input range of 0 v to 2.5 v (if range bit is 1) or 0 v to 5v (if range bit is 0). although the AD7490 is connected to a v dd of 5 v, the serial interface is connected to a 3 v micropro- cessor. the v drive pin of the AD7490 is connected to the same 3v supply of the microprocessor to allow a 3 v logic interface (see digital inputs section.) the conversion result is output in a 16-bit word. this 16-bit data stream consists of four address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data. for applications where
?4 AD7490 rev. a power consumption is of concern, the power-down modes should be used between conversions or bursts of several conversions to improve power performance. (see modes of operation section.) serial interface ad780 2.5v AD7490 0.1 f c/ p 0.1 f 10 f 3v supply 5v supply 0.1 f 10 f a gnd v dd v in 0 v in 15 0v to ref in sclk dout cs din v drive ref in all unused input channels should be connected to gnd figure 11. typical connection diagram analog input any one of 16 analog input channels may be selected for conversion by programming the multiplexer with the address bits add3 C add0 in the control register. the channel configurations are shown in table ii. the AD7490 may also be configured to automatically cycle through a number of channels as selected. the sequencer feature is accessed via the seq and shadow bits in the con trol register (see table iv). the AD7490 can be programmed to continuously convert on a selection of channels in ascending order. the analog input channels to be converted on are selected through programming the relevant bits in the shadow register (see table v). the next serial transfer will then act on the sequence programmed by executing a conversion on the lowest channel in the selection. the next serial transfer will result in a conversion on the next highest channel in the sequence and so on. it is not necessary to write to the control register once a sequencer operation has been initiated. the write bit must be set to zero or the din line tied low to ensure the control register is not accidently overwritten, or the sequence operation interrupted. if the control register is written to at any time during the sequence, then it must be ensured that the seq and shadow bits are set to 1, 0 to avoid interrupting the automatic conversion sequence. this pattern will continue until such time as the AD7490 is written to and the seq and shadow bits are configured with any bit combi- na tion except 1, 0. on com pletion of the sequence, the AD7490 sequencer will return to the first selected channel in the shadow register and commence the sequence again if uninterrupted. rather than selecting a particular sequence of channels, a number of consecutive channels beginning with channel 0 may also be programmed via the control register alone without needing to write to the shadow register. this is possible if the seq and shadow bits are set to 1, 1. the channel address bits add3 through add0 will then determine the final channel in the consecu- tive sequence. the next conversion will be on channel 0, then channel 1 and so on until the channel selected via the address bits add3 through add0 is reached. the cycle will begin again on the next serial transfer provided the write bit is set to low or, if high, that the seq and shadow bits are set to 1, 0; then the adc will continue its preprogrammed automatic se- quence uninterrupted. r egardless of which channel selection method is used, the 16-bit word output from the AD7490 during each conversion will always contain the channel address that the conversion result corresponds to followed by the 12-bit conver- sion result (see serial interface section). digital inputs the digital inputs applied to the AD7490 are not limited by the maximum ratings that limit the analog inputs. instead, the digi- tal inputs applied can go to 7 v and are not restricted by the v dd + 0.3 v limit as on the analog inputs. another advantage of sclk, din, and cs not being restricted by the v dd + 0.3 v limit is the fact that power supply sequencing issues are avoided. if cs , din, or sclk are applied before v dd , then there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 v was applied prior to v dd . v drive the AD7490 also has the v drive feature. v drive controls the voltage at which the serial interface operates. v drive allows the adc to easily interface to both 3 v and 5 v processors. for example, if the AD7490 were operated with a v dd of 5 v, the v drive pin could be powered from a 3 v supply. the AD7490 has better dynamic performance with a v dd of 5 v while still being able to interface to 3 v processors. care should be taken to ensure v drive does not exceed v dd by more than 0.3 v. (see absolute maximum ratings section.) reference section an external reference source should be used to supply the 2.5 v reference to the AD7490. errors in the reference source will result in gain errors in the AD7490 transfer function and will add to the specified full scale errors of the part. a capacitor of at least 0.1 f should be placed on the ref in pin. suitable reference sources for the AD7490 include the ad780, ref193, and the ad1852. if 2.5 v is applied to the ref in pin, the analog input range can either be 0 v to 2.5 v or 0 v to 5 v, depending on the range bit in the control register. modes of operation the AD7490 has a number of different modes of operation. these modes are designed to provide flexible power management options. these options can be chosen to optimize the power dissipation/ throughput rate ratio for differing application requirements. the mode of operation of the AD7490 is controlled by the power management bits, pm1 and pm0, in the control register, as detailed in table iii. when power supplies are first applied to the AD7490, care should be taken to ensure the part is placed in the required mode of operation (see powering up the AD7490 section.)
AD7490 ?5 rev. a 1 14 cs sclk dout din 16 1 14 16 channel identifier bits + conversion result control register is loaded on the first 12 clocks, pm1 1, pm0 1 da ta in to control register to keep part in normal mode, load pm1 1, pm0 1 in control register pa r t is fully powered up once t power up has elapsed pa rt begins to power up on cs rising edge as pm1 1, pm0 1 da ta in to control/shadow register pa r t is in full shutdown t 12 figure 13. full shutdown mode operation 1 cs sclk dout din 16 116116 dummy conversion channel identifier bits + conversion result invalid data channel identifier bits + conversion result da ta in to control/shadow register pa r t enters shutdown on cs rising edge as pm1 0, pm0 1 control register is loaded on the first 12 clocks, pm1 0, pm0 1 da ta in to control/shadow register control register contents should not change, write bit 0 to keep part in this mode, load pm1 0, pm0 1 in control register or set write bit = 0 pa r t is fully powered up pa rt begins to po wer up on cs fa lling edge pa r t enters shutdown on cs rising edge as pm1 0, pm0 1 figure 14. auto shutdown mode operation normal mode (pm1 = pm0 = 1) this mode is intended for the fastest throughput rate performance as the user does not have to worry about any power-up times with the AD7490 remaining fully powered at all times. figure 12 shows the general diagram of the operation of the AD7490 in this mode. 1 12 cs sclk dout din 16 channel identifier bits + conversion result notes 1. control register data is loaded on first 12 sclk cycles 2. shadow register data is loaded on first 16 sclk cycles da ta in to control/shadow register figure 12. normal mode operation the conversion is initiated on the falling edge of cs and the track and hold will enter hold mode as described in the serial interface section. the data presented to the AD7490 on the din line during the first 12 clock cycles of the data transfer is loaded to the control register (provided write bit is 1). if data is to be written to the shadow register (seq 0, shadow 1 on previous write), data presented on the din line during the first 16 sclk cycles is loaded into the shadow register. the part will remain fully pow ered up in normal mode at the end of the conversion as long as pm1 and pm0 are set to 1 in the write transfer during that conver sion. to ensure continued operation in normal mode, pm1 and pm0 are both loaded with 1 on every data transfer. sixteen serial clock cycles are required to complete the conversion and access the conversion result. the track and hold will go back into track on the 14th sclk falling edge. cs may then idle high until the next conversion or may idle low until sometime prior to the next conversion, (effectively idling cs low). once a data transfer is complete ( dout has returned to three- state weak/ tri b it 0), another conversion can be initiated after the quiet time, t quiet , has elapsed by bringing cs low again. full shutdown (pm1 = 1, pm0 = 0) in this mode, all internal circuitry on the AD7490 is powered down. the part retains information in the control register d uring full shutdown. the AD7490 remains in full shutdown until th e power man agement bits in the control register, pm1 and pm0, are changed. if a write to the control register occurs while the part is in full shutdown, with the power management bits changed to pm0 = pm1 = 1, normal mode, the part will begin to power up on the cs rising edge. the track and hold that was in hold while the part was in full shutdown will return to track on the 14th sclk falling edge. to ensure that the part is fully powered up, t power up (t 12 ) should have elapsed before the next cs falling edge. figure 13 shows the general diagram for this sequence. auto shutdown (pm1 = 0, pm0 = 1) in this mode, the AD7490 automatically enters shutdown at the end of each conversion when the control register is updated. when the part is in shutdown, the track and hold is in hold mode. figure 14 shows the general diagram of the operation of the
?6 AD7490 rev. a 1 12 cs sclk dout din 16 1 12 16 1 12 16 dummy conversion channel identifier bits + conversion result invalid data channel identifier bits + conversion result da ta in to control/shadow register pa r t enters standby on cs rising edge as pm1 0, pm0 0 control register is loaded on the first 12 clocks, pm1 0, pm0 0 da ta in to control/shadow register control register should remain unchanged, write bit 0 to keep part in this mode, load pm1 0, pm0 0 in control register pa r t is fully powered up pa rt begins to po wer up on cs fa lling edge pa r t enters standby on cs rising edge as pm1 0, pm0 0 figure 15. auto standby mode operation 1 12 cs sclk dout din 16 1 12 16 1 12 16 dummy conversion dummy conversion invalid data invalid data invalid data da ta in to control correct value in control register valid data from next conversion user can write to shadow register in next conversion keep din line tied high for first two dummy conversions control register is loaded on the first 12 clock edges figure 16. placing into the required operating mode after supplies are applied AD7490 in this mode. in shutdown mode, all internal circuitry on the AD7490 is powered down. the part retains information in the control register during shutdown. the AD7490 remains in shutdown until the next cs falling edge it receives. on this cs falling edge, the track and hold that was in hold while the part was in shutdown will return to track. wake-up time from auto shut- down is 1 s, and the user should ensure that 1 s has elapsed before attempting a valid conversion. when running the AD7490 with a 20 mhz clock, one dummy cycle of 16 sclks should be sufficient to ensure the part is fully powered up. during this dummy cycle, the contents of the control register should remain unchanged; therefore the write bit should be 0 on the din line. this dummy cycle effectively halves the throughput rate of the part, with every other conversion result being valid. in this mode, the power consumption of the part is greatly reduced with the part entering shutdown at the end of each conversion. when the con trol register is programmed to move into auto shutdown, it does so at the end of the conversion. the user can move the adc in and out of the low power state by controlling the cs signal. auto standby (pm1 = pm0 = 0) in this mode, the AD7490 automatically enters standby mode at the end of each conversion when the control register is up dated. figure 15 shows the general diagram of the operation of the AD7490 in this mode. when the part is in standby, portions of the AD7490 are power-down but the on-chip bias generator remains powered up. the part retains information in the control register during standby. the AD7490 remains in standby until it receives the next cs falling edge. on this cs falling edge, the track and hold that was in hold while the part was in standby will return to track. wake-up time from standby is 1 s; the user should ensure that 1 s has elapsed before attempting a valid conversion on the part in this mode. when running the AD7490 with a 20 mhz clock, one dummy cycle of 16 sclks should be sufficient to ensure the part is fully powered up. during this dummy cycle, the contents of the control register should remain unchanged, therefore the write bit should be set to 0 on the din line. this dummy cycle effectively halves the throughput rate of the part with every other conversion result being valid. in this mode, the power consumption of the part is greatly reduced with the part entering standby at the end of each conversion. when the control register is programmed to move into auto standby, it does so at the end of the conversion. the user can move the adc in and out of the low power state by controlling the cs signal. powering up the AD7490 when supplies are first applied to the AD7490, the adc may power up in any of the operating modes of the part. to ensure the part is placed into the required operating mode, the user should perform a dummy cycle operation as outlined in figure 16. the three dummy conversion operations outlined in figure 16 must be performed to place the part into either of the auto modes. the first two conversions of this dummy cycle operation are performed with the din line tied high, and for the third conversion of the dummy cycle operation, the user should write the desired control register configuration to the AD7490 in order to place the part into the required auto mode. on the third cs rising edge after the
AD7490 ?7 rev. a cs sclk dout din 12345613 14 15 16 write seq add3 add2 add1 add0 dontc dontc dontc add3 add2 add1 add0 db11 db10 db2 db1 db0 t convert t 2 t 3 t 9 t 10 t 4 t 7 t 8 t 11 t 5 b four identification bits three- state three- state t q uiet t 6 t 3 b figure 17. serial interface timing diagram cs sclk dout din 12345613141516 add3 add2 add1 add0 db11 db10 db2 db1 db0 t convert t 3 t 9 t 10 t 4 t 7 t 8 t 11 t 5 four identification bits three- state three- state c v in 0v in 1v in 2v in 3v in 4v in 5v in 13 v in 14 v in 15 t 6 t 2 figure 18. writing to shadow register timing diagram supplies are applied, the control register will contain the correct information and valid data will result from the next conversion. therefore, to ensure the part is placed into the correct operating mode when supplies are first applied to the AD7490, the user must first issue two serial write operations with the din line tied high. on the third conversion cycle, the user can then write to the control register to place the part into any of the operating modes. the user should not write to the shadow register until the fourth conversion cycle after the supplies are applied to the adc in order to guarantee the control register contains the correct data. if the user wishes to place the part into either normal mode or full shutdown mode, the second dummy cycle with din tied high can be omitted from the three dummy conversion operation outlined in figure 16. serial interface figure 17 shows the detailed timing diagram for serial interfacing to the AD7490. the serial clock provides the conversion clock and also controls the transfer of information to and from the AD7490 during each conversion. the cs signal initiates the data transfer and conversion process. the falling edge of cs puts the track and hold into hold mode, takes the bus out of three-state, and the analog input is sampled at this point. the conversion is also initiated at this point and will require 16 sclk cycles to complete. the track and hold will go back into track on the 14th sclk falling edge as shown in figure 17 at point b, except when the write is to the shadow register, in which case the track and hold will not return to track until the rising edge of cs , i.e., point c in figure 18. on the 16th s clk falling edge, the dout line will go back into three-state (assuming the weak/ tri bit is set to 0). sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7490. the 12 bits of data are preceded by the four channel address bits add3 to add0, identifying which channel the conversion result corresponds to. cs going low provides address bit add3 to be read in by the microprocessor or dsp. the remaining address bits and data bits are then clocked out by subsequent sclk falling edges beginning with the second address bit add2; thus the first sclk falling edge on the serial clock has address bit add3 provided and also clocks out address b it add2. the final bit in the data transfer is valid on the 16th falling edge, having being clocked out on the previous (15th) falling edge. writing of information to the control register takes place on the first 12 falling edges of sclk in a data transfer, assuming the msb, i.e., the write bit, has been set to 1. if the control register is programmed to use the shadow register, writing of information to the shadow register will take place on all 16 sclk falling edges in the next serial transfer (see figure 18). the shadow reg- ister will be updated upon the rising edge of cs and the track and hold will begin to track the first channel selected in the sequence. if the weak/ tri bit in the control register is set to 1, rather than returning to true three-state upon the 16th sclk falling edge, the dout line will instead be pulled weakly to the logic level corresponding to add3 of the next serial transfer. this is done to ensure that the msb of the next serial transfer is set up in time for the first sclk falling edge after the cs falling edge. if the weak/ tri bit is set to 0 and the dout line has been in true three-state between conversions, then depending on the particular dsp or microcontroller interfacing to the AD7490, address bit add3 may not be set up in time for the dsp/micro to clock it in successfully. in this case, add3 would only be driven from the falling edge of cs and must then be clocked in by the dsp on the following falling edge of sclk. however, if the weak/ tri bit had been set to 1, then although dout is driven with address bit add3 since the last conversion, it is never theless so weakly driven
?8 AD7490 rev. a that another device may still take control of the bus. it will not lead to a bus contention (e.g., a 10 k ? pull-up or pull-down resistor would be sufficient to overdrive the logic level of add3 between conversions) and all 16 channels may be identified. however, if this does happen and another device takes control of the bus, it is not guaranteed that dout will be fully driven to add3 again in time for the read operation w hen control of the bus is taken back. this is especially useful if using an automatic sequence mode to identify to which channel each result corresponds. obviously, if only the first eight channels are in use, then address bit add3 does not need to be decoded, and whether it is successfully clocked in as a 1 or 0 will not matter as long as it is still counted by the dsp/micro as the msb of the 16-bit serial transfer. power versus throughput rate by operating the AD7490 in auto shutdown or auto standby mode, the average power consumption of the adc decreases at lower throughput rates. figure 19 shows how as the throughput rate is reduced, the part remains in its shutdown state longer and the average power consumption over time drops accordingly. for example if the AD7490 is operated in a continuous sampling mode with a throughput rate of 100 ksps and an sclk of 20 mhz (v dd = 5 v), with pm1 = 0 and pm0 = 1, i.e., the device is in auto shutdown mode, then the power consumption is calcu- lated as follows: the maximum power dissipation during normal operation is 12.5 mw (v dd = 5 v). if the power-up time from auto shutdown is one dummy cycle, i.e., 1 s, and the remaining conversion time is another cycle, i.e., 1 s, then the AD7490 can be said to dissipate 12.5 mw for 2 s during each conversion cycle. for the remainder of the conversion cycle, 8 s, the part remains in shutdown m ode. the AD7490 can be said to dissipate 2.5 w for the remaining 8 s of the conversion cycle. if the throughput rate is 100 ksps, the cycle time is 10 s and the average power dissipated during each cycle is 2 10 12 5 8 10 25 2 502 .. mm w+ w= . w when operating the AD7490 in auto standby mode, pm1 = pm0 = 0 at 5 v, 100 ksps, the AD7490 power dissipation is calcu- lated as follows: the maximum power dissipation is 12.5 mw at 5 v during normal operation. again the power-up time from auto standby is one dummy cycle, 1 s, and the remaining conversion time is another dummy cycle, 1 s. the AD7490 dissipates 12.5 mw for 2 s during each conversion cycle. for the remainder of the conversion cycle, 8 s, the part remains in standby mode, dissipating 460 w for 8 s. if the throughput rate is 100 ksps, the cycle time is 10 s and the average power dissipated during each conversion cycle is 2 10 12 5 8 10 460 2 868 . w+ w = . w mm figure 19 shows the power versus throughput rate when using both t he auto shutdown mode and auto standby mode with 5 v supplies. at the lower throughput rates, power consumption for the auto shutdown mode is lower than that for the auto standby mode, with the AD7490 dissipating less power when in shutdown compared to standby. however as the throughput rate is increased, the part spends less time in power-down states, hence difference in power dissipated is negligible between modes. for 3 v supplies, the power consumption of the AD7490 decreases. similar power calculations can be done at 3 v. throughput ?ksps 10 1 0.01 power ?mw 0.1 050 250 100 150 200 350 300 v dd 5v au to standby auto s hutdown figure 19. power vs. throughput rate in auto shutdown and auto standby mode microprocessor interfacing the serial interface on the AD7490 allows the part to be directly connected to a range of many different microprocessors. this section explains how to interface the AD7490 with some of the more common microcontroller and dsp serial interface protocols. AD7490 to tms320c541 the serial interface on the tms320c541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7490. the cs input allows easy interfacing between the tms320c541 and the AD7490 without any glue logic required. the serial port of the tms320c541 is set up to operate in burst mode with inter- nal clkx0 (tx serial clock on serial port 0) and fsx0 (tx frame sync from serial port 0). the serial port control register (spc) must have the following setup: fo = 0, fsm = 1, mcm = 1, and txm = 1. the connection diagram is shown in figure 20. it should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the tms320c541 will provide equidistant sampling. the v drive p in of the AD7490 takes the same supply voltage as that of the tms320c541. this allows the adc to operate at a higher voltage than the serial interface, i.e., tms320c541, if necessary. tms320c541 * AD7490 clkx clkr dr dt fsx fsr v dd sclk dout din cs v drive * additional pins removed for clarity figure 20. interfacing to the tms320c541
AD7490 ?9 rev. a AD7490 to adsp-21xx the adsp-21xx family of dsps are interfaced directly to the AD7490 without any glue logic required. the v drive p in of the AD7490 takes the same supply voltage as that of the adsp-218x. this allows the adc to operate at a higher voltage than the serial interface, i.e., adsp-218x, if necessary. the sport0 control register should be set up as follows: tfsw rfsw 1, alternate framing invrfs invtfs 1, active low frame signal dtype 00, right justify data slen 1111, 16-bit datawords isclk 1, internal serial clock tfsr rfsr 1, frame every word irfs 0 itfs 1 the connection diagram is shown in figure 21. the adsp-218x has the tfs and rfs of the sport tied together, with tfs set as an output and rfs set as an input. the dsp operates in alternate framing mode and the sport control register is set up as described. the frame synchronization signal generated on the tfs is tied to cs , and as with all signal processing applications, equidistant sampling is necessary. however in this example, the timer interrupt is used to control the sampling rate of the adc and under certain conditions, equidistant sampling may not be achieved. the timer register for example is loaded with a value that will provide an interrupt at the required sample interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to control the rfs and thus the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given, (i.e., ax0 tx0), the state of the sclk is checked. the dsp will wait until the sclk has gone high, l ow and high before transmission will start. if the timer and sclk values are chosen such that the instruction to transmit occurs on or near the rising edge of sclk, then the data may be transmitted or it may wait until the next clock edge. for example, if the adsp-2189 with a 20 mhz crystal has an overall master clock frequency of 40 mhz, then the master cycle time would be 25 ns. if the sclkdiv register is loaded with the value 3, a sclk of 5 mhz is obtained, and eight master clock periods will elapse for every 1 sclk period. depending on the throughput rate selected, if the timer registers are loaded with the value 803, 100.5 sclks will occur between interrupts and subsequently between transmit instructions. this situation will result in nonequidistant sampling as the transmit instruction is occurring on a sclk edge. if the number of sclks between interrupts is a figure of n, then equidistant sampling will be implemented by the dsp. adsp-218x * AD7490 sclk dr rfs tfs dt v dd sclk dout cs din v drive * additional pins removed for clarity figure 21. interfacing to the adsp-218x AD7490 to dsp563xx the connection diagram in figure 22 shows how the AD7490 can be connected to the essi (synchronous serial interface) of the dsp563xx family of dsps from motorola. each essi (2 on board) is operated in synchronous mode (syn bit in crb 1) with internally generated 1-bit clock period frame sync for both tx and rx (bits fsl1 0 and fsl0 0 in crb). normal operation of the essi is selected by making mod 0 in the crb. set the word length to 16 by setting bits wl1 1 and wl0 0 in cra. the fsp bit in the crb should be set to 1 so the frame sync is negative. it should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the dsp563xx will provide equidistant sampling. dsp563xx * AD7490 sck srd std sc2 v dd sclk dout cs din v drive * additional pins removed for clarity figure 22. interfacing to the dsp563xx in the example shown in figure 22, the serial clock is taken from the essi so the sck0 pin must be set as an output, sckd 1. the v drive pin of the AD7490 takes the same supply voltage as that of the dsp563xx. this allows the adc to operate at a higher voltage than the serial interface, i.e., dsp563xx, if necessary.
?0 AD7490 rev. a application hints grounding and layout the AD7490 has very good immunity to noise on the power supplies as can be seen by the psrr vs. supply ripple fre quency plot, tpc 3. however, care should still be taken with regard to grounding and layout. the printed circuit board that houses the AD7490 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. a minimum etch technique is generally best for ground planes as it gives the best shielding. all three agnd pins of the AD7490 should be sunk in the agnd plane. digital and analog ground planes should be joined at only one place. if the AD7490 is in a system where multiple devices require an agnd to dgnd connec tion, the connection should still be made at one point only, a star ground point which should be established as close as possible to the AD7490. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the AD7490 to avoid noise coupling. the power supply lines to the AD7490 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum in parallel with 0.1 f capaci tors to agnd. to achieve the best from these decoupling compo nents, they must be placed as close as possible to the device, ideally right up against the device. the 0.1 f capacitors should have low effective series resistance (esr) and effective series induc- tance (esi), such as the common ceramic types or surface mount types, which provide a low impedance path to ground at high frequen cies to handle transient currents due to internal logic switching. pcb design guidelines for chip scale package the lands on the chip scale package (cp-32), are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this will ensure that the solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. on the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. this will ensure that short ing is avoided. thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the pack age. if vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm and the via barrel should be plated with 1 oz. copper to plug the via. the user should connect the printed circuit board thermal pad to agnd. evaluating the AD7490 performance the recommended layout for the AD7490 is outlined in the evaluation board for the AD7490. the evaluation board package includes a fully assembled and tested evaluation board, docu- men tation, and software for controlling the board from the pc via the eval-board controller. the eval-board con troller can be used in conjunction with the AD7490 evaluation board, as well as many other analog devices evalua tion boards ending in the cb designator, to demonstrate/ evaluate the ac and dc performance of the AD7490. the software allows the user to perform ac (fast fourier trans form) and dc (histogram of codes) tests on the AD7490. the software and documentation are on a cd shipped with the evaluation board.
AD7490 ?1 rev. a outline dimensions 28-lead thin shrink small outline package [tssop] (ru-28) dimensions shown in millimeters 4.50 4.40 4.30 28 15 14 1 9.80 9.70 9.60 6.40 bsc pin 1 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 compliant to jedec standards mo-153ae coplanarity 0.10 32-lead frame chip scale package [lfcsp] (cp-32) dimensions shown in millimeters compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 12 max 0.25 ref seating plane 0.05 max 0.02 nom coplanarity 0.08 0.70 max 0.65 nom 1.00 0.90 0.80 1 32 8 9 25 24 16 17 bottom view 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq sq 3.25 3.10 2.95 pin 1 indicator 0.60 max 0.60 max
?2 AD7490 rev. a revision history location page 10/02?ata sheet changed from rev. 0 to rev. a. addition to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to timing specifications notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 change a grade to b grade in absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 addition to ordering guide note 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to typical performance characteristics text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 added new tpc 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 text changes to figures 2 C 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 changes to figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 text changes to figures 11 C 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 addition to analog input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 change to figure 19 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 change to figures 20 C 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 added application hints section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
?3
c02691??0/02(a) printed in u.s.a. ?4

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